The next-generation of VersaClock programmable clock generators from IDT exhibits improved performance over the earlier VersaClock 5, reducing RMS phase jitter from a maximum of 700femtoseconds (fs) to less than 500fs over the integration range of 12kHz to 20MHz.
Kris Rausch, general manager family, multi-market timing, IDT, told a GlobalPress technical briefing that the power consumption has not altered between the iterations. Described as a programmable ASSP, in that it can be programmed and configured before delivery to a customer to meet stringent jitter and phase noise requirements of applications and standards such as 10G Ethernet, enterprise storage SAS and SATA, PCI Express Gen 1/2/3, XAUI, SRIO, stringent PHY reference clocks and the newest generations of high-end FPGAs.
The three devices’ core current consumption of 30 mA, claimed to be about half that of competing devices, eases system thermal constraints and reduces operating power expenses. They are also footprint-compatible with the earlier VersaClock 5 parts, to scale performance with minimal design changes.
Rausch also said the devices enable customers to meet stringent jitter and low power requirements while reducing board space and bill of materials. These features are targeted at markets as diverse as high-end consumer, networking, computing, industrial and communications.”
The programmable clock generator offers universal output pairs that are independently configurable as LVDS, LVPECL, HCSL, or dual LVCMOS and can generate any output frequency from 1.0 to 350MHz on each output pair independently.
The 5P49V6901 has four outputs of any frequency, the 5P49V6913 has two outputs of any frequency while the 5P49V6914 has three outputs of any frequency.
The devices are offered in a 4.0 x 4.0mm 24-VFQFPN package.